Recently, ultra-high-density storage devices using three-dimensional (3D) memory stack structures have been proposed. For example, a three-dimensional NAND memory device may use an array of an alternating stack of insulating materials and spacer material layers that is formed over a substrate containing peripheral devices (e.g., driver/logic circuits). The spacer material layers may be formed as electrically conductive layers, or may be formed as sacrificial material layers that are subsequently replaced with electrically conductive layers. Memory openings are formed through the alternating stack, and are filled with memory stack structures, each of which includes a vertical stack of memory elements and a vertical semiconductor channel.
Typically, vertical semiconductor channels of the memory stack structures are electrically connected to a source line that underlies the alternating stack. In some configurations, the vertical semiconductor channels are connected to the source line through pedestal channel structures that are formed at the bottom of each memory opening. In some other configurations, the source line is formed by replacement of a buried sacrificial material layer that underlies the alternating stack.